1.專利、商標、著作或其他智慧財產權之內容:NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE ANDREADING-OUT METHOD THEREFORE2.專利、商標、著作或其他智慧財產權之取得日期:103/08/183.取得專利、商標、著作或其他智慧財產權之成本:NT$279,0994.其他應敘明事項:In a non-volatile semiconductor memory device outputting a data valuedetermined according to a majority rule by reading-out data from eachmemory cell for an odd number of times, an odd number of latch circuits,each of which comprises a capacitor for selectively holding a voltage ofeach of the data read-out from the memory cell for the odd number of timesin sequence, is provided. The capacitor of each latch circuit is connectedin parallel after the capacitor of each latch circuit selectively holds thevoltage of each of the data read-out from the memory cell for the odd numberof times in sequence, and the data value is determined by the majority rulebased on a composite voltage of the capacitor of each latch circuitconnected in parallel.<摘錄公開資訊觀測站>
1.專利、商標、著作或其他智慧財產權之內容:NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE ANDWRITE-IN METHOD THEREOF2.專利、商標、著作或其他智慧財產權之取得日期:103/07/273.取得專利、商標、著作或其他智慧財產權之成本:NT$794,2644.其他應敘明事項:A non-volatile semiconductor memory device, comprising: a non-volatilememory array, storing multi-values by setting a plurality of differentthreshold voltages for each memory cell, and a control circuit, controllinga write-in operation to the memory cell array. When data have been writteninto the memory cell, the control circuit selects an adjacent word line,uses an erasing level to perform write-in which is weaker than the datawrite-in, and verifies soft programming of the amount of one page, suchthat a narrow-banded erasing level distribution is realized in an adjacentmemory cell.<摘錄公開資訊觀測站>
